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edition 2012-1-11 published by infineon technologies ag 81726 mnchen, germany ? infineon technologies ag 1/11/12. all rights reserved. attention please! the information given in this data sheet shall in no event be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http:// www.infineon.com coolmos ? , coolset ? are trademarks of infineon technologies ag. coolset ? -f3r80 ICE3AR10080CJZ revision history: 2012-1-11 datasheet version 2.0 previous version: 0.1 19 revise typo in tie up resistor at brl pin to disable brownout feature.
type package marking v ds f osc r dson 1) 1) typ @ t=25c 230vac 15% 2) 2) calculated maximum input power rating at t a =50c, t i =125c and without copper area as heat sink. 85-265 vac 2) ICE3AR10080CJZ pg-dip-7 3ar10080cjz 800v 100khz 10.0 w 22w 15w ? ICE3AR10080CJZ version 2.0 3 11 jan 2012 off-line smps current mode controller with integrated 800v coolmos ? and startup cell (brownout & ccm) in dip-7 pg-dip7 c vcc c bulk converter dc output + snubber power management pwm controller current mode 85 ... 270 vac typical application r sense fbb control unit - cs vcc startup cell precise low tolerance peak current limitation drain coolset ? -f3r80 (brownout & ccm) coolmos ? gnd r bo2 r bo1 active burst mode auto restart/ latch mode brownout mode brl r sel features ? 800v avalanche rugged coolmos ? with startup cell ? active burst mode for lowest standby power ? slope compensation for ccm operation ? selectable entry and exit burst mode level ? 100khz internally fixed switching frequency with jittering feature ? auto restart protection for over load, open loop, vcc under voltage & over voltage and over temperature ? external latch enable pin and fast ac reset ? over temperature protection with 50 c hysteresis ? built-in 10ms soft start ? built-in 40ms blanking time for short duration peak power ? propagation delay compensation for both maximum load and burst mode ? brownout feature ? bicmos technology for low power consumption and wide vcc voltage range ? soft gate drive with 50 w turn on resistor description the ice3arxx80cjz is an enhanced version of ice3arxx80jz (coolset ? -f3r80). the pwm controller is based on f3r80 with new and enhanced features. the major new features include slope compensation for ccm operation and fast ac reset after latch enabled. the major enhanced features include fixed voltage brownout detect and voltage detect for the burst selection. in particular it is a device running at 100khz, implemented with brownout features, installing 800v coolmos ? with startup cell and packaged into dip-7. it targets for the low power smps with increased mosfet voltage margin requirement such as off-line battery adapters, dvd r/ w, dvd combi, blue ray, set top box, auxiliary power supply for pc and server, etc. in summary, this enhanced ice3arxx80cjz provides 800v mosfet, lowest standby power, ccm opeation, selectable burst level, brownout feature, maximum power compensated for both maximum and standby load, low emi with frequency jittering and soft gate drive, built-in and flexible protections, etc. therefore, ice3arxx80cjz is a complete solution for the low power smps application. product highlights ? 800v avalanche rugged coolmos ? with startup cell ? ccm and dcm operation with slope compensation ? active burst mode to reach the lowest standby power <100mw ? active burst mode with selectable entry and exit burst mode level ? frequency jitter and soft driving for low emi ? brownout feature ? latch enable and fast ac reset ? auto restart protection for over load, over temperature and over voltage ? pb-free lead plating; rohs compliant
coolset ? -f3r80 ICE3AR10080CJZ table of contents page version 2.0 4 11 jan 2012 1 pin configuration and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.1 pin configuration with pg-dip-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.2 pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2 representative blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.2 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.3 improved current mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.3.1 pwm-op . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.3.2 pwm-comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.3.3 slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.4 startup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.5 pwm section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.5.1 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.5.2 pwm-latch ff1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.5.3 gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.6 current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.6.1 leading edge blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.6.2 combined opp curve considering propagation delay and slope compen- sation 14 3.7 control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.7.1 active burst mode (patented) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.7.1.1 selectable burst entry level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.7.1.2 entering active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.7.1.3 working in active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.7.1.4 leaving active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.7.2 protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3.7.2.1 vcc ovp, otp, external protection enable and vcc under voltage . . .18 3.7.2.2 over load, open loop protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.7.3 brownout mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 3.7.4 fast ac reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.3.1 supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.3.2 internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.3.3 pwm section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.3.4 soft start time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.3.5 control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 4.3.6 current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
coolset ? -f3r80 ICE3AR10080CJZ version 2.0 5 11 jan 2012 4.3.7 coolmos ? section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 5 coolmos ? perfromance characteristic . . . . . . . . . . . . . . . . . . . . . . . . . .26 6 input power curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 7 outline dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 8 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 9 schematic for recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . .31
version 2.0 6 11 jan 2012 coolset ? -f3r80 ICE3AR10080CJZ pin configuration and functionality 1 pin configuration and functionality 1.1 pin configuration with pg-dip-7 figure 1 pin configuration pg-dip-7 (top view) 1.2 pin functionality brl (brownout, fast ac reset & latch enable) the brl pin combines the functions of brownout, fast ac reset and the external latch enable. the brownout feature is to stop the switching pulse when the input voltage is dropped to lower than 1v. the fast ac reset feature is to recover from latch feature when the voltage of brl pin has a rising rate of <1.33v/ms from 0.4v to 1v. the external latch enable function is an external access to stop the gate switching and force the ic to enter latch mode. it is triggered by pulling the pin voltage to less than 0.4v. fbb (feedback & burst entry select) the fbb pin combines the feedback function and the burst entry/exit control. the regulation information is provided by the fbb pin to the internal protection unit and the internal pwm-comparator to control the duty cycle. the fbb-signal is the only control signal in case of light load at the active burst mode. the burst entry select provides an access to select the entry/exit burst mode level. cs (current sense) the current sense pin senses the voltage developed on the shunt resistor inserted in the source of the integrated coolmos ? . if cs reaches the internal threshold of the current limit comparator, the driver output is immediately switched off. furthermore the current information is provided for the pwm- comparator to realize the current mode operation. drain (drain of integrated coolmos ? ) the drain pin is the connection to the drain of the integrated coolmos ? . vcc (power supply) the vcc pin is the power supply of the ic. the voltage operating range is between 10.5v and 24.7v. gnd (ground) the gnd pin is the ground of the controller. pin symbol function 1 brl brownout, fast ac reset & latch enable 2 fbb feedback & burst entry/exit con- trol 3 cs current sense/ 800v coolmos ? source 4 n.c. not connected 5 drain 800v coolmos ? drain 6 - (no pin) 7 vcc controller supply voltage 8 gnd controller ground package pg-dip-7 1 7 8 4 3 2 5 gndbrl fbb cs vcc n.c. drain
coolset ? -f3r80 ICE3AR10080CJZ representative blockdiagram version 2.0 7 11 jan 2012 2 representative blockdiagram figure 2 representative blockdiagram
coolset ? -f3r80 ICE3AR10080CJZ functional description version 2.0 8 11 jan 2012 3 functional description all values which are used in the functional description are typical values. for calculating the worst cases the min/max values which can be found in section 4 electrical characteristics have to be considered. 3.1 introduction ice3arxx80cjz brownout and ccm 800v version is an enhanced version of the coolset ? -f3r80. the major new and enhanced features include slope compensation for ccm operation, fast ac reset after latch enabled, fixed voltage brownout detect and voltage detect for the burst selection. it is particular good for high voltage margin low power smps application such as auxiliary power supply for pc and server. the major characteristics are that the ic is developed with 800v coolmos ? with start up cell, having adjustable brownout feature, running at 100khz switching frequency, ccm operation and packed in dip-7 package. the features include bicmos technology to reduce power consumption and increase the vcc voltage range, cycle by cycle current mode control, built-in 10ms soft start to reduce the stress of switching elements during start up, built-in 40ms for short period of peak power before entering protection, active burst mode for lowest standby power, propagation delay compensation for close power limit between high line and low line which also takes into consideration of slope compensation, frequency jittering for low emi performance, the built-in auto-restart mode protections for open loop, over load, vcc ovp, vcc under voltage, and latch enable feature etc. the other features include narrowing the feedback voltage swing to 0.3v (from 0.5v) during burst mode so that the output voltage ripple can be reduced by 40%, reduction of the fast voltage fall time of the mosfet by increasing the soft turn-on time and addition of 50 w turn-on resistor, faster start up time by optimizing the vcc capacitor to 10uf and over temperature protection with 50c hysteresis. the new features include slope compensation for stable operation in ccm mode when duty is larger than 0.5, fixed voltage triggering for the bronwout feature for easier design, voltage levels select for entry/exit burst level, fast ac reset fto reset the latch feature, etc. in summary, the coolset ? ice3arxx80cjz provides good voltage margin of mosfet, lowest standby power, flexible burst level, ccm operation, reduced output ripple during burst mode, accurate power limit for both maximum power and burst power, low emi with frequency jittering and soft gate drive, built-in and flexible protections, etc. therefore, coolset ? ice3arxx80cjz is a complete solution for the low power smps application. 3.2 power management figure 3 power management the undervoltage lockout monitors the external supply voltage v vcc . when the smps is plugged to the main line the internal startup cell is biased and starts to charge the external capacitor c vcc which is connected to the vcc pin. this vcc charge current is controlled to 1.0ma by the startup cell. when the v vcc exceeds the on-threshold v ccon =17v the bias circuit are switched on. then the startup cell is switched off by the undervoltage lockout and therefore no power losses present due to the connection of the startup cell to the drain voltage. to avoid uncontrolled ringing at switch-on, a hysteresis start up voltage is implemented. the switch-off of the controller can only take place when v vcc falls below 10.5v after normal operation was entered. the maximum current consumption before the controller is activated is about 210 m a. when v vcc falls below the off-threshold v ccoff =10.5v, the bias circuit is switched off and the soft start counter is reset. thus it ensures that at every startup cycle the soft start starts at zero. the internal bias circuit is switched off if latched off mode or auto restart mode is entered. the current consumption is then reduced to 420 m a. once the malfunction condition is removed, this block will then turn back on. the recovery from auto restart mode does not require re-cycling the ac line. in case latched off mode is entered, vcc needs to be lowered below 8v or having ac fast reset triggered to reset the internal bias voltage reference power management latched off mode reset; v vcc < 8v or ac fast reset is triggered 5.0v latched off mode undervoltage lockout 17v 10.5v power-down reset active burst mode auto restart mode startup cell vcc drain coolmos ? soft start block
coolset ? -f3r80 ICE3AR10080CJZ functional description version 2.0 9 11 jan 2012 latched off mode. this is done usually by re-cycling the ac line. when active burst mode is entered, the internal bias is switched off most of the time but the voltage reference is kept alive in order to reduce the current consumption below 620 m a. 3.3 improved current mode figure 4 current mode current mode means the duty cycle is controlled by the slope of the primary current. this is done by comparing the fbb signal with the amplified current sense signal. figure 5 pulse width modulation in case the amplified current sense signal exceeds the fbb signal the on-time t on of the driver is finished by resetting the pwm-latch (figure 5). the primary current is sensed by the external series resistor r sense inserted in the source of the integrated coolmos ? . by means of current mode regulation, the secondary output voltage is insensitive to the line variations. the current waveform slope will change with the line variation, which controls the duty cycle. the external r sense allows an individual adjustment of the maximum source current of the integrated coolmos ? . to improve the current mode during light load conditions the amplified current ramp of the pwm-op is superimposed on a voltage ramp, which is built by the switch t2, the voltage source v1 and a resistor r1 (see figure 6). every time the oscillator shuts down for maximum duty cycle limitation the switch t2 is closed by v osc . when the oscillator triggers the gate driver, t2 is opened so that the voltage ramp can start. figure 6 improved current mode in case of light load the amplified current ramp is too small to ensure a stable regulation. in that case the voltage ramp is a well defined signal for the comparison with the fbb-signal. the duty cycle is then controlled by the slope of the voltage ramp. by means of the time delay circuit which is triggered by the inverted v osc signal, the gate driver is switched-off until it reaches approximately 156ns delay time (figure x3.25 pwm op improved current mode 0.6v c8 pwm-latch cs fbb r s q q driver soft-start comparator t fbb amplified current signal t on t 0.6v driver pwm op 0.6v 10k ? oscillator c8 t 2 r 1 fbb pwm-latch v 1 gate driver voltage ramp v osc soft-start comparator time delay circuit (156ns) x3.25 pwm comparator
coolset ? -f3r80 ICE3AR10080CJZ functional description version 2.0 10 11 jan 2012 7). it allows the duty cycle to be reduced continuously till 0% by decreasing v fbb below that threshold. figure 7 light load conditions 3.3.1 pwm-op the input of the pwm-op is applied over the internal leading edge blanking to the external sense resistor r sense connected to pin cs. r sense converts the source current into a sense voltage. the sense voltage is amplified with a gain of 3.25 by pwm op. the output of the pwm-op is connected to the voltage source v 1 . the voltage ramp with the superimposed amplified current signal is fed into the positive inputs of the pwm- comparator c8 and the soft-start-comparator (figure 8). 3.3.2 pwm-comparator the pwm-comparator compares the sensed current signal of the integrated coolmos ? with the feedback signal v fbb (figure 8). v fbb is created by an external optocoupler or external transistor in combination with the internal pull-up resistor r fb and provides the load information of the feedback circuitry. when the amplified current signal of the integrated coolmos ? exceeds the signal v fbb the pwm-comparator switches off the gate driver. figure 8 pwm controlling 3.3.3 slope compensation due to the sub harmonic oscillation of ccm operation when duty cycle is larger than 50%, the slope compensation is added. the slope mc; 50mv/ m s is added to the current sense pin when gate is on. during burst mode operation, the mc slope is shut down and no slope added into the current sense signal. this can save the power consumption at burst mode. figure 9 slope compesnation t t v osc 0.6v fbb t max. duty cycle gate driver voltage ramp 156ns time delay x3.25 pwm op improved current mode pwm comparator cs soft-start comparator 5v c8 0.6v fbb optocoupler r fb pwm-latch x3.25 pwmop gate drive signal c8 0.62v m c =50mv/us slope compensation pwm comparator s5 5.0v 10k ? d2 1pf leb 180/220ns r slope fb active burst mode pwmlatch cs
coolset ? -f3r80 ICE3AR10080CJZ functional description version 2.0 11 11 jan 2012 3.4 startup phase figure 10 soft start in the startup phase, the ic provides a soft start period to control the primary current by means of a duty cycle limitation. the soft start function is a built-in function and it is controlled by an internal counter. . figure 11 soft start phase when the v vcc exceeds the on-threshold voltage, the ic starts the soft start mode (figure 11). the function is realized by an internal soft start resistor, an current sink and a counter. and the amplitude of the current sink is controlled by the counter (figure 12). figure 12 soft start circuit after the ic is switched on, the v softs voltage is controlled such that the voltage is increased step- wisely (32 steps) with the increase of the counts. the soft start counter would send a signal to the current sink control in every 300 m s such that the current sink decrease gradually and the duty ratio of the gate drive increases gradually. the soft start will be finished in 10ms (t soft-start ) after the ic is switched on. at the end of the soft start period, the current sink is switched off. within the soft start period, the duty cycle is increasing from zero to maximum gradually (see figure 13). figure 13 gate drive signal under soft-start phase soft-start com parator soft start & g7 c 7 g ate driver 0.6v x3.25 pw m o p cs soft start counter soft start s o f t s t a r t f i n i s h softs v s o fts v s o fts 2 v s o fts 1 5v r softs soft start counter i 2i 4i softs 8i 32i t v softs32 v softs gate driver t t soft-start
coolset ? -f3r80 ICE3AR10080CJZ functional description version 2.0 12 11 jan 2012 in addition to start-up, soft-start is also activated at each restart attempt during normal auto restart. figure 14 start up phase the start-up time t start-up before the converter output voltage v out is settled, must be shorter than the soft- start phase t soft-start (figure 14). by means of soft-start there is an effective minimization of current and voltage stresses on the integrated coolmos ? , the clamp circuit and the output rectifier and it helps to prevent saturation of the transformer during start-up. 3.5 pwm section figure 15 pwm section block 3.5.1 oscillator the oscillator generates a fixed frequency of 100khz with frequency jittering of 4% (which is 4 khz) at a jittering period of 4ms. a capacitor, a current source and current sink which determine the frequency are integrated. the charging and discharging current of the implemented oscillator capacitor are internally trimmed in order to achieve a very accurate switching frequency. the ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle limitation of d max =0.75. once the soft start period is over and when the ic goes into normal operating mode, the switching frequency of the clock is varied by the control signal from the soft start block. then the switching frequency is varied in range of 100khz 4 khz at period of 4ms. 3.5.2 pwm-latch ff1 the output of the oscillator block provides continuous pulse to the pwm-latch which turns on/off the integrated coolmos ? . after the pwm-latch is set, it is reset by the pwm comparator, the soft start comparator or the current -limit comparator. when it is in reset mode, the output of the driver is shut down immediately. t t v s o fts t v s o fts 3 2 4.5v t s o ft-s ta rt v o u t v fb v o u t t s ta rt-u p oscillator duty cycle max gate driver 0.75 clock & g9 1 g8 pwm section ff1 r s q soft start comparator pwm comparator current limiting coolmos ? gate frequency jitter soft start block
coolset ? -f3r80 ICE3AR10080CJZ functional description version 2.0 13 11 jan 2012 3.5.3 gate driver figure 16 gate driver the driver-stage is optimized to minimize emi and to provide high circuit efficiency. this is done by reducing the switch on slope when exceeding the integrated coolmos ? threshold. this is achieved by a slope control of the rising edge at the driver?s output (figure 17) and adding a 50 w gate turn on resistor (figure 16). thus the leading switch on spike is minimized. figure 17 gate rising slope furthermore the driver circuit is designed to eliminate cross conduction of the output stage. during power up, when vcc is below the undervoltage lockout threshold v vccoff , the output of the gate driver is set to low in order to disable power transfer to the secondary side. 3.6 current limiting figure 18 current limiting block there is a cycle by cycle peak current limiting operation realized by the current-limit comparator c10. the source current of the integrated coolmos ? is sensed via an external sense resistor r sense . by means of r sense the source current is transformed to a sense voltage v sense which is fed into the pin cs. if the voltage v sense exceeds the internal threshold voltage v csth, the comparator c10 immediately turns off the gate drive by resetting the pwm latch ff1. a propagation delay compensation is added to support the immediate shut down of the integrated coolmos ? with very short propagation delay. thus the influence of the ac input voltage on the maximum output power can be reduced to minimal. this compensation applies to both the peak load and burst mode. in order to prevent the current limit from distortions caused by leading edge spikes, a leading edge blanking (leb) is integrated in the current sense path for the comparators c10, c12 and the pwm-op. the output of comparator c12 is activated by the gate g6 if active burst mode is entered. when it is activated, the current limiting is reduced to v csth_burst . this voltage level determines the maximum power level in active burst mode. vcc 1 pwm-latch coolmos ? gate driver gate 50 ? t (internal) v gate 4.6v typ. t = 160ns current limiting c10 c12 & g6 propagation-delay compensation v csth pwm latch ff1 10k d1 1pf pwm-op propagation-delay compensation-burst v csth_burst cs leb 220ns leb 18 0ns s4 c5 v fb_burst fbb or g8 active burst mode
coolset ? -f3r80 ICE3AR10080CJZ functional description version 2.0 14 11 jan 2012 3.6.1 leading edge blanking figure 19 leading edge blanking whenever the integrated coolmos ? is switched on, a leading edge spike is generated due to the primary- side capacitances and reverse recovery time of the secondary-side rectifier. this spike can cause the gate drive to switch off unintentionally. in order to avoid a premature termination of the switching pulse, this spike is blanked out with a time constant of t leb = 220ns for normal load and t leb = 180ns for burst mode. 3.6.2 combined opp curve considering propagation delay and slope compensation the ice3arxx80cjz has combined the propagation delay, ccm inherit reduced power effect and the slope compensation effect for the overcurrent control. it employs the dynamic threshold voltage v csth with 2 steps slope compensation to achieve the closed over current for whole input voltage range. in case of overcurrent detection, there is always propagation delay to switch off the integrated coolmos ? . an overshoot of the peak current i peak is induced to the delay, which depends on the ratio of di/ dt of the peak current (figure 20). figure 20 current limiting the overshoot of signal2 is larger than of signal1 due to the steeper rising waveform. this change in the slope is depending on the ac input voltage. propagation delay compensation is integrated to reduce the overshoot due to di/dt of the rising primary current. thus the propagation delay time between exceeding the current sense threshold v csth and the switching off of the integrated coolmos ? is compensated over temperature within a wide input range. current limiting is then very accurate. for the inherit influence of the ccm operation, the final vcs can not be constant in whole line range as in dcm. this ice3arxx80cjz has implemented with 2 compensation curves for the compensation so that the maximum power can be close. one of the curve is used when the time range is larger than 4 m s and the other is for lower than 4 m s. the propagation delay compensation is realized by means of a dynamic threshold voltage v csth (figure 21). in case of a steeper slope the switch off of the driver is earlier to compensate the delay. figure 21 dynamic voltage threshold v csth a typical measured vsense vs dvsense/dt is plotted in figure 22 for reference. figure 22 overcurrent shutdown t v sense v csth t leb = 220ns/180ns t i sense i limit t propagation delay i overshoot1 i peak1 signal1signal2 i overshoot2 i peak2 t v csth v osc signal1 signal2 v sense propagation delay max. duty cycle off time t
coolset ? -f3r80 ICE3AR10080CJZ functional description version 2.0 15 11 jan 2012 similarly, the same concept of propagation delay compensation is also implemented in burst mode with reduced level, v csth_burst (figure 18). with this implementation, the entry and exit burst mode power can be close between low line and high line input voltage. 3.7 control unit the control unit contains the functions for active burst mode, auto restart mode and latch mode. the active burst mode, latch mode and the auto restart mode both have internal blanking time. with the blanking time, the ic avoids entering into those two modes accidentally. those buffer time is very useful for the application which works in short duration of peak power occasionally. 3.7.1 active burst mode (patented) to increase the efficiency of the system at light load, the most effective way is to operate at burst mode. starting from coolset ? f3, the ic has been employing the active burst mode and it can achieve the lowest standby power. ice3arxx80cjz adopts the same concept with some more innovative improvements to the feature. it includes the adjustable entry burst level, close power control between high line and low line and the smaller output ripple during burst mode. most of the burst mode design in the market will provide a fixed entry burst mode level which is a ratio to the maximum power of the design. ice3arxx80cjz provides a more flexible level which can be selected externally. propagation delay is the major contributor for the power control variation for dcm flyback converter. it is proved to be effective in the maximum power control. ice3arxx80cjz also apply the same concept in the burst mode. therefore, the entry and exit burst mode power is also finely controlled during burst mode. the feedback control swing during burst mode will affect the output ripple voltage directly. ice3arxx80cjz reduces the swing to 0.3v (from 0.5v). therefore, it would have around 40% improvement for the output ripple. figure 23 active burst mode the active burst mode is located in the control unit. figure 23 shows the related components. 3.7.1.1 selectable burst entry level the burst mode entry level can be selected by changing the different resistor r sel at fbb pin. there are 3 levels to be selected with different resistor which are targeted for 15%, 10% and 5% of the maximum input power. at the same time, the exit burst level are targeted to 27%, 20% and 11% of the maximum power accordingly. the below table is the control logic for the entry and exit level with the fbb voltage. level v fbb r sel 1 v fbb < v ref1 (1.8v) < 405k w 2 v ref1 (1.8v) v ref2 (4.0v) > 1530k w entry level exit level level % of p in_max v fb_burst % of p in_max v csth_burst 1 5% 1.29v 11% 0.21v 2 10% 1.61v 20% 0.29v 3 15% 1.84v 27% 0.34v c6a 3.5v c13 4.0v control unit internal bias c6b 3.2v & g11 active burst mode c5 20 ms blanking time c12 cs v csth_burst v fb_burst g6 & ff1 fbb current limiting burst detect and adjust r sel
coolset ? -f3r80 ICE3AR10080CJZ functional description version 2.0 16 11 jan 2012 during ic first startup, the ref good signal is logic low when vcc<8v. the low ref good signal will reset the burst mode level detection latch. when the burst mode level detection latch is low and ic is in off state, the fbb resistor is isolated from the fbb pin and a current source i sel (3.5 ma ) is turned on instead. from vcc=8v to vcc on threshold(17v), the fbb pin will start to charge to a voltage level associated with r sel resistor. when vcc reaches vcc on threshold, the fbb voltage is sensed. the burst mode thresholds are then chosen according to the fbb voltage level. the burst mode level detection latch is then set to high. once the detection latch is set high, any change of the fbb level will not change the threshold level. when vcc reaches vcc on threshold, a timer of 2 m s is started. after the 2 m s ends, the i sel is turned off while the fbb resistor is connected to fbb pin (figure 24). figure 24 burst mode detect and adjust 3.7.1.2 entering active burst mode the fbb signal is kept monitoring by the comparator c5 (figure 23). during normal operation, the internal blanking time counter is reset to 0. when fbb signal falls below v fb_burst , it starts to count. when the counter reaches 20ms and fbb signal is still below v fb_burst , the system enters the active burst mode. this time window prevents a sudden entering into the active burst mode due to large load jumps. after entering active burst mode, a burst flag is set and the internal bias is switched off in order to reduce the current consumption of the ic to about 620 m a. it needs the application to enforce the vcc voltage above the undervoltage lockout level of 10.5v such that the startup cell will not be switched on accidentally. or otherwise the power loss will increase drastically. the minimum vcc level during active burst mode depends on the load condition and the application. the lowest vcc level is reached at no load condition. 3.7.1.3 working in active burst mode after entering the active burst mode, the fbb voltage rises as vout starts to decrease, which is due to the inactive pwm section. the comparator c6a monitors the fbb signal. if the voltage level is larger than 3.5v, the internal circuit will be activated; the internal bias circuit resumes and starts to provide switching pulse. in active burst mode the gate g6 is released and the current limit is reduced to vcsth_burst (figure 2 and 23). in one hand, it can reduce the conduction loss and the other hand, it can reduce the audible noise. if the load at vout is still kept unchanged, the fbb signal will drop to 3.2v. at this level the c6b deactivates the internal circuit again by switching off the internal bias. the gate g11 is active again as the burst flag is set after entering active burst mode. in active burst mode, the fbb voltage is changing like a saw tooth between 3.2v and 3.5v (figure 25). 3.7.1.4 leaving active burst mode the fbb voltage will increase immediately if there is a high load jump. this is observed by the comparator c13 (figure 23). since the current limit is reduced to 0.21v~0.34v during active burst mode, it needs a certain load jump to rise the fbb signal to exceed 4.0v. at that time the comparator c5 resets the active burst mode control which in turn blocks the comparator c12 by the gate g6. the maximum current can then be resumed to stabilize v out. fbb selection logic v dd v csth_burst v fb_burst i sel ref good uvlo control unit s 1 s 2 2 s delay r s burst mode detection latch r s e l compare logic v ref1 v ref2 r fb
coolset ? -f3r80 ICE3AR10080CJZ functional description version 2.0 17 11 jan 2012 figure 25 signals in active burst mode 3.7.2 protection modes the ic provides auto restart mode as the major protection feature. auto restart mode can prevent the smps from destructive states. there are 3 kinds of auto restart mode; normal auto restart mode, odd skip auto restart mode and non switch auto restart mode. odd skip auto restart mode (figure 26) is that there is no detect of fault and no switching pulse for the odd number restart cycle. at the even number of restart cycle the fault detect and soft start switching pulses are maintained. if the fault persists, it would continue the auto-restart mode. however, if the fault is removed, it can release to normal operation only at the even number auto restart cycle . figure 26 odd skip auto restart waveform non switch auto restart mode is similar to odd skip auto restart mode except the start up switching pulses are also suppressed at the even number of the restart cycle. the detection of fault still remains at the even number of the restart cycle. when the fault is removed, the ic will resume to normal operation at the even number of the restart cycle (figure 27). figure 27 non switch auto restart waveform the main purpose of the odd skip auto restart is to extend the restart time such that the power loss during auto restart protection can be reduced. this feature is particularly good for smaller vcc capacitor where the restart time is shorter. v fb_burst 3.5v 4.0v v fbb t t v csth_burst v csth v cs 10.5v v vcc t t 620ua i vcc t 3.4ma v out t 20ms blanking time current limit level during active burst mode 3.2v entering active burst mode blanking timer leaving active burst mode 10.5v t v cs t v vcc 17v fault detected no detect startup and detect no detect 10.5v t v cs t v vcc 17v fault detected no detect startup and detect no detect no switching
coolset ? -f3r80 ICE3AR10080CJZ functional description version 2.0 18 11 jan 2012 the following table lists the possible system failures and the corresponding protection modes. 3.7.2.1 vcc ovp, otp, external protection enable and vcc under voltage figure 28 vcc ovp, otp, external protection enable vcc ovp condition is when v vcc voltage is > 25.5v, the ic enters into odd skip auto restart mode (figure 28). the over temperature protection otp is sensed inside the controller ic. the thermal shutdown block keeps on monitoring the junction temperature of the controller. after detecting a junction temperature higher than 130c, the ic will enter into the non switch auto restart mode. the ice3arxx80cjz has also implemented with a 50 c hysteresis. that means the ic can only be recovered when the controller junction temperature is dropped 50 c lower than the over temperature trigger point (figure 28). the external latch enable feature can provide a flexibility to a customer?s self-defined protection feature. this function can be triggered by pulling down the v brl voltage to < 0.4v. or it can simply trigger the base pin of an external transistor, t le at the brl pin. when this function is enabled, it will enter into latch mode after 210 m s blanking time. the gate drive is stopped and there is no switching pulse before it is recovered . the vcc undervoltage and short opto-coupler will go into the normal auto restart mode inherently. in case of vcc undervoltage, the vcc voltage drops indefinitely. when it drops below the vcc under voltage lock out ?off? voltage (10.5v), the ic will turn off the ic and the startup cell will turn on again. then the vcc voltage will be charged up to uvlo ?on? voltage (17v) and the ic turns on again provided the startup cell charge up current is not drained by the fault. if the fault is not removed, the vcc will continue to drop until it hits uvlo ?off? voltage and the restart cycle repeats. short optocoupler can lead to vcc undervoltage because once the opto-coupler (transistor side) is shorted, the feedback voltage will drop to zero and there will be no switching pulse. then the vcc voltage will drop same as the vcc undervoltage. 3.7.2.2 over load, open loop protection figure 29 over load and open loop protection in case of overload or open loop, the v fbb voltage exceeds 4.5v which will be observed by comparator c4. then the built-in blanking time counter starts to count. when it reaches 40ms, the odd skip auto restart mode is activated (figure 29). 3.7.3 brownout mode when the ac input voltage is removed, the voltage at the bulk capacitor will fall. when it reaches a point that the system is greater than the system allowed maximum power, the system may go into over load protection. however, this kind of protection is not expected for some of the applications such as auxiliary power for pc/server system because the output is in hiccup mode due to over load protection (auto restart mode). the brownout mode is to eliminate this phenomenon. the ice3arxx80cjz will sense the vcc over voltage odd skip auto restart mode over load odd skip auto restart mode open loop odd skip auto restart mode vcc undervoltage normal auto restart mode short optocoupler normal auto restart mode over temperature non switch auto restart mode external protection enable latch mode voltage reference control unit auto restart mode reset v vcc < 10.5v latch enable signal t le c9 0.4v stop gate drive spike blanking 30s thermal shutdown t j >130c brl auto restart mode c2 120s blanking time 25.5v 210s blanking time latch mode vcc c4 4.5v control unit auto restart mode fbb 40ms blanking time r fb 5.0v
coolset ? -f3r80 ICE3AR10080CJZ functional description version 2.0 19 11 jan 2012 input ac voltage to the brl pin by an ac hold up circuit and 2 potential divider resistors. in some applications, it needs the ic to continue to work for certain time when ac voltage is disconnected. after that, the ic will stop working. if the brownout connection is taping from the bulk capacitor, the delay time is too short. therefore, it needs the brown out detetction at the ac input (figure 30). the c br0 is charged up by ac line voltage through r bo0 , which is then fed to brl pin through a voltage divider. when the ac voltage drops, if the brl pin voltage is lower than 1v for 270 m s, the ice3arxx80cjz will go into brownout mode. if, however, the ac line goes up again, the brl voltage will be larger than 1.25v and the ice3arxx80cjz will leave brown out mode and recover to normal operation. the brownout mode is default ?on? during the system starts up. when the system is powered up, the bulk capacitor and the vcc capacitor are charged up at the same time. when the vcc voltage is charged to >8v, the brownout circuit starts to operate (figure 30). since the uvlo is still at low level as the vcc voltage does not reach the 17v uvlo ?on? voltage. the nand gate g20 will release a low signal to the flip flop ff2 and the negative output of ff2 will release a high signal. hence it is in brownout mode during the system starts up. figure 30 brownout detection circuit once the system enters the brownout mode, there will be no switching pulse and the ic enters into another type auto-restart mode which is similar to the protection auto-restart mode but the ic will monitor the brl signal in each restart cycle (figure 31). figure 31 brownout mode waveform if the brownout feature is not needed, it needs to tie the brl pin to the vcc pin through a current limiting resistor, 5m w ~10m w . the brl pin cannot be in floating condition. 3.7.4 fast ac reset during normal operation, the ice3arxx80cjz can be latched by pulling down the brl voltage below 0.4v for 210 m s. there are 2 condtions to reset the latch feature. the first one is to pull down the vcc voltage to below 8v. however, the vcc drop would take quite a long time if it is by normal ac power down. the second one is to have a slow rise time of the brl voltage from 0.4v to 1v for at least 450 m s after the brl pin is pulled down. this timing can be achieved by the ac recycle. and it is also called the fast ac reset (figure 32). figure 32 latch and fast ac reset figure 33 shows different latch and reset cases. case a : not latched (solid line); the timing below 0.4v is 150 m s and is less than 210 m s. c1a control unit brownout mode brl r bo1 r bo2 vac uvlo q r s ff2 g20 g21 c1b q 1.25v 1v r bo0 c br0 blanking time 270 s 10.5v t v cs t v vcc 17v brownout detected startup and detect bbl voltage control unit r bo1 r bo2 vac r bo0 c br0 latch enable signal t le c3 0.4v latch mode latch reset c2a c2b 0.4v blanking time 450 s & 1v c11 8v vcc g3 g2 blanking time 210us brl
coolset ? -f3r80 ICE3AR10080CJZ functional description version 2.0 20 11 jan 2012 case b : latched (dashed line); the timing below 0.4v is 450 m s which is larger than 210 m s. no latch reset as the rise time from 0.4v to 1v is 300 m s which is less than the 450 m s. case c : latched and reset (dotted line); the timing below 0.4v is 710 m s which is larger than 210 m s. but the rise time from 0.4v to 1v is 560 m s which is larger than the latch reset blanking time of 450 m s. figure 33 latch and fast ac reset example 0.4v t v brl 1v 150 s not latched (a) 450 s 300 s 560 s latched (b) latched and reset (c) 710 s
coolset ? -f3r80 ICE3AR10080CJZ electrical characteristics version 2.0 21 11 jan 2012 4 electrical characteristics note: all voltages are measured with respect to ground (pin 8). the voltage levels are valid if other ratings are not violated. 4.1 absolute maximum ratings note: absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. for the same reason make sure, that any capacitor that will be connected to pin 7 ( v cc) is discharged before assembling the application circuit. t a =25 c unless otherwise specified. parameter symbol limit values unit remarks min. max. drain source voltage v ds - 800 v pulse drain current, t p limited by t jmax i d_puls - 1.10 a avalanche energy, repetitive t ar limited by max. t j =150c 1) 1) repetitive avalanche causes additional power losses that can be calculated as p av = e ar * f e ar - 0.011 mj avalanche current, repetitive t ar limited by max. t j =150c i ar - 0.44 a vcc supply voltage v vcc -0.3 27 v fbb voltage v fbb -0.3 5.5 v brl voltage v brl -0.3 5.5 v cs voltage v cs -0.3 5.5 v junction temperature t j -40 150 c controller & coolmos ? storage temperature t s -55 150 c thermal resistance junction -ambient r thja - 96 k/w soldering temperature, wavesoldering only allowed at leads t sold - 260 c 1.6mm (0.063in.) from case for 10s esd capability (incl. drain pin) v esd - 2 kv human body model 2) 2) according to eia/jesd22-a114-b (discharging a 100pf capacitor through a 1.5k w series resistor)
coolset ? -f3r80 ICE3AR10080CJZ electrical characteristics version 2.0 22 11 jan 2012 4.2 operating range note: within the operating range the ic operates as described in the functional description. 4.3 characteristics 4.3.1 supply section note: the electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range t j from ? 25 c to 125 c. typical values represent the median values, which are related to 25c. if not otherwise stated, a supply voltage of v cc = 17 v is assumed. parameter symbol limit values unit remarks min. max. vcc supply voltage v vcc v vccoff 24.7 v max value limited due to vcc ovp junction temperature of controller t jcon -25 130 c max value limited due to thermal shut down of controller junction temperature of coolmos ? t jcoolmos -25 150 c parameter symbol limit values unit test condition min. typ. max. start up current i vccstart - 210 300 m a v vcc =16v vcc charge current i vcccharge1 - - 5.0 ma v vcc = 0v i vcccharge2 0.55 1.0 1.60 ma v vcc = 1v i vcccharge3 0.38 0.75 - ma v vcc =16v leakage current of start up cell and coolmo s ? i startleak - 0.2 50 m a v drain = 650v at t j =100c 1) 1) the parameter is not subjected to production test - verified by design/characterization supply current with inactive gate i vccsup1 - 1.9 3.2 ma supply current with active gate i vccsup2 - 3.4 4.8 ma i fbb = 0a supply current in latched off mode with inactive gate i vcclatch - 420 - m a i fbb = 0a supply current in auto restart mode with inactive gate i vccrestart - 420 - m a i fbb = 0a supply current in active burst mode with inactive gate i vccburst1 - 620 950 m a v fbb = 2.5v i vccburst2 - 620 950 m a v vcc = 11.5v, v fbb = 2.5v vcc turn-on threshold vcc turn-off threshold vcc turn-on/off hysteresis v vccon v vccoff v vcchys 16.0 9.8 - 17.0 10.5 6.5 18.0 11.2 - v v v
coolset ? -f3r80 ICE3AR10080CJZ electrical characteristics version 2.0 23 11 jan 2012 4.3.2 internal voltage reference 4.3.3 pwm section 4.3.4 soft start time parameter symbol limit values unit test condition min. typ. max. trimmed reference voltage v ref 4.90 5.00 5.10 v measured at pin fbb i fbb = 0a parameter symbol limit values unit test condition min. typ. max. fixed oscillator frequency f osc1 87 100 113 khz f osc2 92 100 108 khz t j = 25c frequency jittering range f jitter - 4.0 - khz t j = 25c frequency jittering period t jitter - 4.0 - ms t j = 25c max. duty cycle d max 0.70 0.75 0.80 min. duty cycle d min - - 0 v fbb < 0.3v pwm-op gain a v 3.17 3.25 3.33 voltage ramp offset v offset-ramp - 0.60 - v v fbb operating range min level v fbmin - 0.7 - v v fbb operating range max level v fbmax - - 4.4 v d v sense / d t = 0.134v/ m s , limited by comparator c4 1) 1) the parameter is not subjected to production test - verified by design/characterization fbb pull-up resistor r fb 9.0 15.4 22.0 k w slope compensation rate m c 45 50 55 mv/ m s cs=0v parameter symbol limit values unit test condition min. typ. max. soft start time t ss - 10 - ms
coolset ? -f3r80 ICE3AR10080CJZ electrical characteristics version 2.0 24 11 jan 2012 4.3.5 control unit parameter symbol limit values unit test condition min. typ. max. brownout reference voltage for comparator c1a v bo_l 1.14 1.25 1.36 v brownout reference voltage for comparator c1b v bo_e 0.91 1 1.09 v leakage current of brl pin i leakage -0.5 - 0.5 ma blanking time to enter brownout mode v bkc1b 190 270 310 m s fast ac reset voltage for comparator c2a v c2a 0.3 0.4 0.5 v fast ac reset voltage for comparator c2b v c2b 0.91 1 1.09 v blanking time for comparator c2a v bkc2a 315 450 585 m s charging current to select burst mode i sel 2.8 3.5 4.2 ma burst mode selection reference voltage v ref1 1.69 1.80 1.91 v v ref2 3.78 4.00 4.22 v over load limit for comparator c4 v fbc4 4.40 4.50 4.72 v active burst mode entry level for comparator c5 15% p in_max v fb_burst1 1.77 1.84 1.91 v v fbb >v ref2 10% p in_max v fb_burst2 1.50 1.61 1.72 v v ref1 coolset ? -f3r80 ICE3AR10080CJZ electrical characteristics version 2.0 25 11 jan 2012 note: the trend of all the voltage levels in the control unit is the same regarding the deviation except v vccovp . 4.3.6 current limiting 4.3.7 coolmos ? section 1) the parameter is not subjected to production test - verified by design/characterization. the thermal shutdown temperature refers to the junction temperature of the controller. parameter symbol limit values unit test condition min. typ. max. peak current limitation v csth1 0.69 0.73 0.77 v d v sense / d t = 0.41v/ m s v csth2 0.72 0.76 0.80 v d v sense / d t = 0.134v/ m s peak current limitation in active burst mode 27% p in_max v csth_burst1 0.313 0.34 0.368 v v fbb >v ref2 20% p in_max v csth_burst2 0.264 0.29 0.320 v v ref1 coolset ? -f3r80 ICE3AR10080CJZ coolmos ? perfromance characteristic version 2.0 26 11 jan 2012 5 coolmos ? perfromance characteristic figure 34 safe operating area (soa) curve for ICE3AR10080CJZ figure 35 soa temperature derating coefficient curve
coolset ? -f3r80 ICE3AR10080CJZ coolmos ? perfromance characteristic version 2.0 27 11 jan 2012 figure 36 power dissipation; p tot =f(t a ) figure 37 drain-source breakdown voltage; v br(dss) =f(t j ), i d =0.25ma
coolset ? -f3r80 ICE3AR10080CJZ input power curve version 2.0 28 11 jan 2012 6 input power curve two input power curves giving the typical input power versus ambient temperature are showed below; vin=85vac~265vac (figure 38) and vin=230vac+/-15% (figure 39). the curves are derived based on a typical discontinuous mode flyback model which considers either 60% maximum duty ratio or 150v maximum secondary to primary reflected voltage (higher priority). the calculation is based on no copper area as heatsink for the device. the input power already includes the power loss at input common mode choke, bridge rectifier and the coolmos.the device saturation current ( i d_puls @ t j =125c) is also considered. to estimate the output power of the device, it is simply multiplying the input power at a particular operating ambient temperature with the estimated efficiency for the application. for example, a wide range input voltage (figure 38), operating temperature is 50c, estimated efficiency is 85%, then the estimated output power is 12w (15w * 85%). figure 38 input power curve vin=85~265vac; p in =f(t a ) figure 39 input power curve vin=230vac+/-15%; p in =f(t a )
coolset ? -f3r80 ICE3AR10080CJZ outline dimension version 2.0 29 11 jan 2012 7 outline dimension figure 40 pg-dip-7 (pb-free lead plating plastic dual-in-line outline) pg-dip-7 (plastic dual in-line outline)
coolset ? -f3r80 ICE3AR10080CJZ marking version 2.0 30 11 jan 2012 8 marking figure 41 marking for ICE3AR10080CJZ marking
coolset ? -f3r80 ICE3AR10080CJZ schematic for recommended pcb layout version 2.0 31 11 jan 2012 9 schematic for recommended pcb layout figure 42 schematic for recommended pcb layout general guideline for pcb layout design using f3 coolset (refer to figure 42): 1. ?star ground ?at bulk capacitor ground, c11: ?star ground ?means all primary dc grounds should be connected to the ground of bulk capacitor c11 separately in one point. it can reduce the switching noise going into the sensitive pins of the coolset device effectively. the primary dc grounds include the followings. a. dc ground of the primary auxiliary winding in power transformer, tr1, and ground of c16 and z11. b. dc ground of the current sense resistor, r12 c. dc ground of the coolset device, gnd pin of ic11; the signal grounds from c13, c14, c15 and collector of ic12 should be connected to the gnd pin of ic11 and then ?star ?connect to the bulk capacitor ground. d. dc ground from bridge rectifier, br1 e. dc ground from the bridging y-capacitor, c4 2. high voltage traces clearance: high voltage traces should keep enough spacing to the nearby traces. otherwise, arcing would incur. a. 400v traces (positive rail of bulk capacitor c11) to nearby trace: > 2.0mm b. 600v traces (drain voltage of coolset ic11) to nearby trace: > 2.5mm 3. filter capacitor close to the controller ground: filter capacitors, c13, c14 and c15 should be placed as close to the controller ground and the controller pin as possible so as to reduce the switching noise coupled into the controller. guideline for pcb layout design when >3kv lightning surge test applied (refer to figure 42): 1. add spark gap spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated charge during surge test through the sharp point of the saw-tooth plate. a. spark gap 3 and spark gap 4, input common mode choke, l1: gap separation is around 1.5mm (no safety concern)
coolset ? -f3r80 ICE3AR10080CJZ schematic for recommended pcb layout version 2.0 32 11 jan 2012 b. spark gap 1 and spark gap 2, live / neutral to ground: these 2 spark gaps can be used when the lightning surge requirement is >6kv. 230vac input voltage application, the gap separation is around 5.5mm 115vac input voltage application, the gap separation is around 3mm 2. add y-capacitor (c2 and c3) in the live and neutral to ground even though it is a 2-pin input 3. add negative pulse clamping diode, d11 to the current sense resistor, r12: the negative pulse clamping diode can reduce the negative pulse going into the cs pin of the coolset and reduce the abnormal behavior of the coolset. the diode can be a fast speed diode such as in4148. the principle behind is to drain the high surge voltage from live/neutral to ground without passing through the sensitive components such as the primary controller, ic11.
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